ZCU102 GTR Lanes

Owned by Russell Joyce (Deactivated)
Last updated: 20 Sept, 2017
Unless otherwise stated, everything on this page is based on Vivado 2017.2 and a ZCU102 Revision 1.0 board with ES2 silicon (EK-U1-ZCU102-ES2-G).

The Zynq UltraScale+ device on the ZCU102 has four GTR (high-speed transceiver) lanes, which can be assigned to PCIe (up to x4), SATA, USB3 and DisplayPort (up to x2).

The ZCU102 board supports PCIe Gen2 x1 by default, however x2 and x4 are possible by modifying some settings in Vivado (for the FSBL), and correctly setting the external GTR switch (see page 86 of the user guide).

For Linux, the GTR switch setting at boot time can be controlled in the device tree. The device tree also needs modifying to remove the DP/SATA/USB3 devices if these are disabled so the PCIe can use their GTR lanes.

Changing GTR lane assignments in Vivado

In the Zynq configuration decides can be enabled or disabled, and the number of lanes selected (for PCIe and DP).

Ensure the clocks are still correctly set after this, especially if a device has been disabled then re-enabled (check against board preset).

Removing devices from Linux device tree

To avoid issues, the following entries need to be removed (or commented-out) in zynqmp-zcu102.dts when disabled in the FSBL:

  • SATA - &sata (entire block)
  • DisplayPort - &xlnx_dp, &xlnx_dp_sub, &xlnx_dp_snd_pcm0, &xlnx_dp_snd_pcm1, &xlnx_dp_snd_card, &xlnx_dp_snd_codec0, &xlnx_dpdma (entire blocks)
  • USB3 - &dwc3_0 (leave block with status and dr_mode in order to still use USB2 with no GTR PHY).

Changing the GTR multiplexer

The ZCU102 contains a GTR multiplexer external to the Zynq chip, in order to redirect GTR lanes to the appropriate interface. This is controlled using a GPIO expander over I2C, as detailed in the board manual.

Theoretically, this could be set in U-Boot using i2c commands, however interference from the MSP430 system management controller seems to disrupt access to this bus unless physically held in reset.

However, the Linux device tree entry for the GPIO expander can be used to set its default pin levels for the required GTR lane settings at boot time, by editing the gtr_selX entries of tca6416_u97 in zynqmp-zcu102.dts.