You will find the Vitis HLS Knowledge Base useful as it contains tips and reminders. Remember to always use the HLS component template from the previous practical.
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Once your hardware is working, use the directives in HLS to optimise the design. You must aim for a design with a latency below 900 clock cycles (it is possible to get down to around 200-300 with some work). Don't worry about how much hardware you are using. Go straight for speed!
When you have completed this task show a demonstrator who will mark it as completed in your logbook.
Tips:
- You will want to use the
ARRAY_PARTITIONdirective to split up your arrays, because if they are implemented using BRAMs then can only support 2 accesses in parallel. If you apply this to a multidimensional array you will need to set the dimension to 0 for the tools to partition all dimensions. - Your hardware should use the contents of its input grid to determine the state of a completely new grid, and return that new grid. If you try to keep it all in one grid and start editing it 'live' you'll get incorrect results.