Page Comparison

The S3ESK VGA Core provides a 3-bit (eight colour) display output at 640x480, 800x600 or 1024x768 for the Spartan-3E Starter Boards used in the EMBS module.

...

• Load your project in XPS
• Select Project | Rescan User Repositories.
• Select the 'IP Catalog' tab on the left-hand side, and expand 'Project Local PCores' then 'EMBS'. You should see a component called 'VGA Core'.
• Double click this component and answer 'Yes' then 'OK' (the sections below on resolution and pixel width explain how the settings here can be changed, but for now the defaults are fine).
• Select the 'System Assembly View' tab then 'Bus Interfaces'.
• Find the 'embs_vga_0' component  component and expand it by clicking the +
• It has two bus connections, MPLB (master PLB) and SPLB (slave PLB). Use the drop down boxes to connect these both to mb_plb.
• Click the 'Addresses' tab and click the 'Generate Addresses' button. (A yellow icon on its own in the top right)
• Click the 'Ports' tab and expand the 'embs_vga_0' component by clicking the +
• Select the 'Red', 'Green', 'Blue', 'HSync' and 'VSync' connections (NOT 'not Pixel_Clk'), right click and select 'Make External' from the menu. The 'Connected Port' column for each signal should automatically fill in with a value starting with 'External Ports::embs_vga_0_' followed  followed by the signal name and '_pin'. This connects the five VGA signals to external ports (it routes them to outside the FPGA).
• Now select Hardware | Launch Clock Wizard
• A dialogue may appear telling you "The following clock ports are editable...". Click OK.
• Find the 'embs_vga_0' component  component and set its 'Pixel_Clk' frequency  frequency to 40.000000 MHz 000000 MHz (you may have to type this if it is not in the drop-down list). This value will be different if a different output resolution is chosen (see below).
• Click Validate Clocks. It should say "Clock Validations were successful!".
• Click OK. Click OK on the "Please make sure..." box that appears.

We have finished connecting up the VGA component inside the FPGA.
The last final thing we need to do it to tell the tools which external pins on the FPGA to use for the Red, Green, Blue, HSync and VSync signals, and to relax the timing constraints between the PLB and pixel clocks (so the static timing analysis phase doesn't moan at us).

• Open your project's User Constraints File by double-clicking 'UCF File' in the 'Project Files' list of the 'Project' window in XPS (alternatively, open <your XPS project>/data/system.ucf in a text editor).
• Scroll to the bottom of the file and copy and paste the following in to into it:

# EMBS VGA Core
NET "embs_vga_0_Red_pin" LOC = "H14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "embs_vga_0_Green_pin" LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "embs_vga_0_Blue_pin" LOC = "G15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "embs_vga_0_HSync_pin" LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "embs_vga_0_VSync_pin" LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
PIN "embs_vga_0.MPLB_Clk" TNM_NET = clk1;
PIN "embs_vga_0.Pixel_Clk" TNM_NET = clk2;
TIMESPEC TS_clk1_clk2 = FROM "clk1" TO "clk2" 10 ns DATAPATHONLY;
TIMESPEC TS_clk2_clk1 = FROM "clk2" TO "clk1" 10 ns DATAPATHONLY;.Pixel_Clk" TNM_NET = clk2;
TIMESPEC TS_clk1_clk2 = FROM "clk1" TO "clk2" 10 ns DATAPATHONLY;
TIMESPEC TS_clk2_clk1 = FROM "clk2" TO "clk1" 10 ns DATAPATHONLY;

• • The NET constraints tell the tools where each signal should be routed and the logic level type to use; e.g. connect embs_vga_0_Red_pin to pin H14 on the FPGA chip, which is routed on the board to the red pin of the VGA socket, and use TTL (5V) logic signals.
  • The TIMESPEC constraint tells to tools to allow up to 10ns of difference between the bus and pixel clock domains used by the core, which run at different speeds - this is fine as the data is buffered using asynchronous FIFOs within the core.
• Save and close the UCF file.
• Click Hardware | Generate Bitstream.
• Re-export your design to SDK.
• In SDK, right click on your BSP and select Board Support Package Settings.
• Select Drivers. 'embs_vga_0' should be in the list. If it is not, close and re-open SDK.
• Set the driver of 'embs_vga_0' to 'generic' and click OK.

Core options

The following options can be changed from the peripheral settings in XPS (accessed by double clicking the instance of the core in your project).

Output resolution

...

A note on memory bandwidth

While a VGA core set to 1024x768 resolution at 8 bits-per-pixel will function fine if it is the only part of the system accessing DDR, it uses a lot of memory and PLB bandwidth. If your system is experiencing delays accessing the PLB or DDR, or the graphics output has problems, try reducing the resolution or bits-per-pixel values. As a rough guide to relative PLB and memory utilisation, the following table shows the number of bytes read from DDR per second for each configuration.

...

The file contains functions for 4- and 8-bit output, and allows the screen resolution to be set, so make sure the constants at the top of the file are correct before use.

FPGA Resource Usage

On a Spartan-3E xc3s500e (the FPGA that is on the Starter Board), Xilinx ISE estimates the core usage at: