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The HDMI output uses DMA to copy data directly from the DDR. To allow this, you will need a high-performance AXI slave port on the Zynq Processing System.
As we are using S_AXI_HP0 for HLS components /wiki/spaces/RTS/pages/35689890, using S_AXI_HP1 for the HDMI will give the best performance, and avoid adding unnecessary additional bus logic to the FPGA fabric.
The script should enable this interface for you, but from this point on you will need to be careful in connection automation dialogs to ensure that the HDMI and HLS components use the correct interfaces.
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Data is stored in the frame buffer using 32 bits per pixel. Each colour component takes one byte, with the highest byte unused, followed by red, blue and green. This gives a pixel format of 0x00RRBBGG0x00RRGGBB.
Remember to flush the caches after changing the frame buffer, so data is written back to DDR for the hardware to use. If writing the entire buffer, completely flushing the caches with Xil_DCacheFlush() will be more efficient than flushing a region, as the caches are significantly smaller than the frame buffer.
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