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A note on memory bandwidth
While a VGA core set to 1024x768 resolution at 8 bits-per-pixel will function fine if it is the only part of the system accessing DDR, it uses a lot of memory and PLB bandwidth. If your system is experiencing delays accessing the PLB or DDR, or the graphics output has problems, try reducing the resolution or bits-per-pixel values. As a rough guide to relative PLB and memory utilisation, the following table shows the number of bytes read from DDR per second for each configuration.
| Resolution | Bits per pixel | Bytes read per second |
|---|---|---|
| 640x480 | 4 | 9,216,000 |
| 640x480 | 8 | 18,432,000 |
| 800x600 | 4 | 14,400,000 |
| 800x600 | 8 | 28,800,000 |
| 1024x768 | 4 | 23,592,960 |
| 1024x768 | 8 | 47,185,920 |
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The file contains functions for 4- and 8-bit output, and allows the screen resolution to be set, so make sure the constants at the top of the file are correct before use.
FPGA Resource Usage
On a Spartan-3E xc3s500e (the FPGA that is on the Starter Board), Xilinx ISE estimates the core usage at:
| Logic Utilisation | Used | Available | Utilisation |
|---|---|---|---|
| Number of Slices | 373 | 4,656 | 8% |
| Number of Slice Flip Flops | 437 | 9,312 | 4% |
| Number of 4 input LUTs | 528 | 9,312 | 5% |
| Number of bonded IOBs | 0 | 232 | 0% |
| Number of BRAMs | 1 | 20 | 5% |